For Release January 15, 2001
For more information, contact:
Georgia Marszalek, ValleyPR for InTime, (650) 345-7477, georgia@valleypr.com
www.intime-online.com
InTime’s DesignWarrior IMPROVES
CHIP PERFORMANCE, CUT DESIGN TIME
Collaborative, Performance-Predictive Integrated Development Environment Attacks
Design Productivity and Performance Gaps with Its Specification to Physical Implementation Views
Virtual Prototyping Guides Design Teams to Develop RTL for Faster, More Predictable Silicon
CUPERTINO, Calif., USA, January 15, 2001, InTime Software, Inc. (InTime), a new EDA company, today announced its first product, DesignWarriorTM, an Integrated RTL Development Environment coupled with Automated Implementation Flows, that improves chip performance by guiding design teams to develop better Register-Transfer Level (RTL) designs.
DesignWarrior shaves weeks from RTL design cycles. Its virtual prototyping capabilities are used to inject WireAwarenessTM into the RTL code. Its technology makes performance prediction possible before a single line of RTL is developed and continues refining the prediction until the RTL code is completed. This prediction is possible because the design specification, as it evolves, is automatically mapped directly to a silicon technology, alleviating the requirement for logic designers to be physical design experts in order to successfully tape-out.
Automated Implementation Flows drive simulation, synthesis and place and route tools such as those from Cadence Design Systems (NYSE: CDN) and Synopsys (Nasdaq: SNPS). DesignWarrior is aware of the different views (logical, synthesis, and physical) of a design enabling it determine the points in the hierarchy from where the design should be simulated, synthesized or placed and routed. It automatically sets up the parameters, rules, and constraints, based on the estimations derived during the virtual prototyping phase, to drive these processes. It develops timing budgets for the blocks in the design and drives the implementation flow, all transparently to the designer.
“Our goal is to address the design performance gap with a predictive virtual prototyping environment that improves design productivity with fully automated physical generation, partitioning, budgeting and implementation,” said George Janac, company founder and president.
Janac noted, “Today’s complex designs require larger teams and there is nothing on the horizon that will eliminate this. DesignWarrior allows these large teams to collaborate more effectively by automating the pushing and pulling of design information across the team. This saves time because lack of visibility across the design is a key problem which often leads to unnecessary design iterations that result from miscommunication among team members.”
Target Market
DesignWarrior is for system companies, IDMs and semiconductor vendors involved in the design of complex ASICs, ASSPs and SOCs. These companies have tremendous time to market pressures as well as above average performance and complexity requirements. Janac added, “We have seen companies who struggle to achieve target performances as low at 66MHz. So our environment is really for anyone who is trying to surpass performance objectives or is simply tired of thrashing between the RTL, synthesis and layout to improve performance.”
More About DesignWarrior
DesignWarrior includes InSight, the designer’s desktop, a Technology Wizard and a Project Wizard.
InSight provides designers with RTL design entry capability, virtual prototyping, auto-piloted implementation flows and fully automated RTL design planning. Inputs to DesignWarrior are design specifications, partial or complete RTL and constraints in industry standard formats such as SDC. The Project Wizard is used to describe the team make up, the design goals, such as area, speed and performance and evaluate the target technology against the design specifications. The Technology Wizard automatically creates design kits using industry standard formats such as LEF, DEF, .lib and STAMP.
What’s New
Virtual Prototyping, Automated Design Planning , and Prediction
At any stage during the design’s development, DesignWarrior predicts the performance of the design using its virtual prototyping, or automated design planning engine. This prediction process is ongoing as the design progresses through implementation.
Collaboration
DesignWarrior provides for automated design team collaboration. During the design process, designers need to update the rest of the team with their changes and then update their local designs with the global changes. This communication occurs automatically whenever a change needs to be propagated.
DesignWarrior automatically gathers data from the project definition, other parts of the design and other designers. With this information designers can chat about, negotiate, tag and resolve issues related to the team’s design.
Pricing and Availability
DesignWarrior is available in March. It runs on Sun workstations and supports Verilog.
Pricing begins at $85,000 (USD).
About InTime
InTime was founded in 1999 with the goal of developing EDA design and design planning technologies that help close the electronic design performance and design productivity gaps.
InTime is headquartered at 10131 Bubb Rd., Cupertino, CA 95014. For more information call
408-0565-0111 or visit www.intime-online.com.
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Acronyms and Definitions
AIF: Automatic Implementation Flow
ASIC: Application Specific IC
ASSP: Application Specific Standard Part
DEF Design Exchange Format
EDA: Electronic Design Automation
EEMS: Engineering Enterprise Management System
IC: Integrated Circuit
IDE: Integrated Design Environment
IDM: Integrated Device Manufacturer
.lib Library format (Synopsys)
LEF: Library Exchange Format
RTL: Register-Transfer Level or RT Language, a design description above gate-level netlists
SDC: Synopsys Design Constraints
SOC: System-on-Chip
STAMP: static timing analysis modeling format (Synopsys)
Verilog: popular hardware description language
About the Performance and Productivity Gaps
The EDA industry continues to face obstacles to realizing the potential of IC process technology the IC Performance Gap and the Productivity Gap. The former deals with the fact that the same process geometry, i.e., 1.5micron, can yield 1.5GHz microprocessors but only 100-250MHz ASICs. The latter deals with the growing complexity of designs today and the inability of current day EDA tools to manage the complexity well.
DesignWarrior and WireAwareness are trademarks of InTime Software, Inc.
All other tradenames and trademarks are the property of their respective owners.
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